1. Field of the Invention
The present invention relates to a memory control device and memory control method capable of reducing charge/discharge current consumed during inputs of various commands to a semiconductor memory device and reducing occurrence of power noises.
2. Description of Related Art
Due to miniaturization of portable electric appliances of these days, there have increased the number of multi-chip-package-type semiconductor devices and that of system-in-package-type semiconductor devices wherein plural chips are built in a single package. Since plural chips are built in a single package, heat and power noises occur at the plural chips.
For preventing heat in a package, it is required to reduce current consumption at each chip. Especially, a synchronous dynamic random access memory (abbreviated as SDRAM hereinafter) and the like increase current consumption due to large volume design. Therefore, reduce of current consumption is important. Since conventional memory control devices for controlling data access to an SDRAM did not have control function for lowering current consumption at an SDRAM, a clock enable signal CKE was always kept in active state and a clock signal was constantly inputted while an SDRAM was in active state. Since a clock signals was constantly inputted, an internal circuit in an SDRAM continued to consume power and additionally, charge/discharge of wiring capacity held by wirings between an SDRAM and a memory control device consumed power, as well. Those were problems. JP Laid-open Patent Publication No. 2000-29779 discloses countermeasure to resolve the above-described problem and, FIG. 21 and FIG. 22 show a block diagram of an image processing device (memory control device) and a timing chart of the device, respectively. As shown in FIG. 21, an SDRAM control circuit 902b changes state of a clock enable signal CKE from inactive state change to active state while the SDRAM control circuit 902b receives an imaging start signal and an output start signal and the image processing device completes imaging or data outputting. A clock enable signal CKE is also supplied to a gate signal generator circuit 902d to generate a gate signal for turning a clock signal ON/OFF and a gate signal is supplied to a clock driver 903. The clock driver 903 changes state of a clock signal from stop-operation state to start-operation state while a clock enable signal CKE in active state changes into active state, that is, while input and output of image data are executed. Furthermore, when state of a clock enable signal CLK changes from active state to inactive state, the clock driver 903 changes state of a clock signal CLK from start-operation state to stop-operation state. As shown in FIG. 22, an image data write start signal WriteStart changes state of a clock enable signal CKE from inactive state to active state and also changes state of a clock signal from stop-operation state change to start-operation state. By supplying command signals such as bank active, write, pre-charge and the like and a write image data signal Data, image data can be written on an SDRAM 901. In the image processing device directed to JP Laid-open Patent Publication No. 2000-29779, a clock signal CLK is supplied to the SDRAM in response to a clock enable signal CKE state of which changes to active state during input/output of image data to an SDRAM. A clock signal CLK is stopped without input/output of image data so that operation of an internal circuit in an SDRAM is stopped to reduce power consumption at the internal circuit and to reduce power consumption due to wiring capacity held by wiring between an SDRAM and a memory control device.
Furthermore, according to normal specification of SDRAM, the number of sense amplifiers to be activated concurrently is made different between a refresh operation period and a normal operation period. For example, in a 64MSDRAM, the number of sense amplifiers to be activated concurrently at the time of auto-refresh period and self-refresh period is 16(k) while it is 4(k) at the time of normal operation period. Since refresh operation must be completed within a predetermined period so as to avoid data destruction, the number of sense amplifiers to be activated concurrently at the time of refreshment is set to a large number.